Communication switching system computer memory control arrangement

ABSTRACT

A computer memory control arrangement includes a plurality of input/output ports for permitting a central processor connected to one port to access a main memory to obtain or store data or instructions for enabling the central processor to effect call processing or maintenance operations and for permitting the transfer of programs to the main memory from a drum control memory including at least one drum control unit connected to a another port. A port select circuit permits port selection on a priority basis when memory requests are received over more than one port simultaneously. In addition, while the memory request for a selected port is being processed, the selection of a second port for a second memory request can be initiated before the end of the memory cycle for the first selected port. Each drum control unit has an assigned block of data storage locations serving as an initialization table within the computer main memory. The central processor can effect a transfer of instructions and/or data words from a designated drum control unit to the main memory by accessing the main memory and storing instructions in the initialization table for the designated drum control unit and thereafter sending an instruction to the drum control unit to enable the drum control unit to access its initialization table and effect the transfer indicated therein. Initialization table protection is provided by a circuit which prevents one drum control unit from writing into an initialization table of another drum control unit. A read only memory circuit prevents the drum control units and the central processor from writing into a preselected block of data storage locations of the main memory. In addition, a software protect read only memory circuit prevents the central processor from writing into blocks of data storage locations of the computer main memory while permitting the drum control units to write into such locations.

United States Patent [1 Fleming et al.

Kasimir W. Schild, Needham Heights, Mass.

[73] Assignee: GTE Automatic Electric Laboratories Incorporated, Northlake, 111.

[22] Filed: June 15, 1973 [2]} Appl. No.: 370,573

[52] US. Cl. 340/1725 [51] Int. Cl. G06F 9/18 [58] Field of Search 340/1725 [56] References Cited UNITED STATES PATENTS 3,275,991 9/1966 Schneberger 340/1725 3,525,081 8/1970 Flemming, Jr. et al.. 340/1725 3,525,985 8/1970 Melliar-Smith 340/1725 3.569.938 3/1971 Eden et a1 340/1725 3.581291 5/1971 lwamoto et al. 340/1725 3,588,829 6/1971 Boland et a1 340/1725 3,611,315 10/1971 Murano et al. 340/1725 3,618,040 1 1/1971 lwamoto et al. 340/1725 3,701,107 10/1972 Williams 340/1725 3,705,388 12/1972 Nishimoto 340/1725 3,771,137 11/1973 Barrier et al. 340/1725 Primary E.taminer.l0seph M. Thesz, Jr.

[57] ABSTRACT A computer memory control arrangement includes a plurality of input/output ports for permitting a central [4 1 Oct. 28, 1975 processor connected to one port to access a main memory to obtain or store data or instructions for enabling the central processor to effect call processing or maintenance operations and for permitting the transfer of programs to the main memory from a drum control memory including at least one drum control unit connected to a another port. A port select circuit permits port selection on a priority basis when memory requests are received over more than one port simultaneously. In addition, while the memory request for a selected port is being processed, the selection of a second port for a second memory request can be initiated before the end of the memory cycle for the first selected port. Each drum control unit has an assigned block of data storage locations serving as an initialization table within the computer main memory. The central processor can effect a transfer of instructions and/or data Words from a designated drum control unit to the main memory by accessing the main memory and storing instructions in the initialization table for the designated drum control unit and thereafter sending an instruction to the drum control unit to enable the drum control unit to access its initialization table and effect the transfer indicated therein. lnitiali zation table protection is provided by a circuit which prevents one drum control unit from writing into an initialization table of another drum control unit. A read only memory circuit prevents the drum control units and the central processor from writing into a preselected block of data storage locations of the main memory. In addition, a software protect read only memory circuit prevents the central processor from writing into blocks of data storage locations of the computer main memory while permitting the drum control units to write into such locations.

5 Claims, 25 Drawing Figures uzuonv com. CM 10 a FROM M aus M1335 ucuomr g [1 WEB-l) nuoness our: CONTROL nsrunn MA ADDRESS mum: muss sus H MEMORY a CONTROL W om com can nus mun) mum! ADDIIEss 22%;; m INTERFACE T0 a mom "(mm-L PORT 2,4,6 lunar coumu. RETURN CODE m mud] uauonv ax 55L 1,2,3 5 4 nm ADDRESS lounzss nus souac: ENABLE A Q CONTROL DATA 8J5 S01E25 BIABLE E g PORY 1 INK ENABLE STATUS T0 1: Fnnu CON-mm m uzuont curnot LINESJNTERRUPFS T0 ccP-n conrnol. mum: Wm

ncrunu ADDRESS nolnzss mm, m g N PORT '6 culc A can CONTROL CONTROL IN T L ET RII 1" DATA FOR I T MISHATCH RETURN PORT a FCOITROL m A 8K Sn 5". PORT SEL /M 1 015mm BK SEL CONTROL Pom SEL SHAPLEX TIMING m5 .A a B CONTROL m 1 ADDRESS r: L m -cMc-a om cnur uruomr CONTROL RETURN a IN ctgn tgot CONTROL in mm 1 ("up H CONTROL serum: RT 2 4 6 mum" pen 9 cannot in mm a sum AM To a wgf CONTROL azrurm sruss LINES mrennums j I; FRO" ADDRESS BUS suuncs PORT .5 "no" L MILE mu nus source 9 e um com 7 CONTROL m m M" ENABLE smx ENABLEJ utuonv RETURN 55L DRESS law-2,4 coma ADDRESS um usuonv contact RETURN l CONTROL mmmc: out In zg zx z m 7 "m 1| um nus (um-Bl Aunnsss a Hep To u FROM J comm m Emmet Hm I H ADDRESS nus Hill-Bl cm nccooi: "no,"

'Q QB Aoonzss om comm. RETURN/ BANK: 1.2,! a 4 US. Patent DATA BUS SOURCE Sheet 8 of 21 ENABLE To PORTS l-8 NAIN MEM. INTERFACE BK I DATA BUS sINI DCU DR(00-25)(3|,32) A FROM SEL(PT l-7] DATA BUS DIsT (4'42) FIes.I3-Is" PoRTs 3,4,5,6 I f BUFFER T0 [5 52, ADDREss B us (61,62) *MLTX COMPARATOR -cDNPR ABIOO-ITI'UIZK T TO DCU (00-25) r INTERFACE DATA BUS MT. (0009) 0.2) IN -MLTX 2 DB DATA CMC B (00-25) BUS PORTS DDI00-25I I 2 COLLECTOR T0 I m A GATES DATA BUS -ML 3 DB DAT/A coNPARAToR (2'32) (O025) BUS 3'52; 661;: III; -ccP HUGO-25)] BUFF cNIc DATA sus,

To MAIN MENU-41 INTERrAcE FIG.5

DATA B15 (0025) /306 DATA EVEN PAR BUS DATA BUS PARITY 00-25 DDD PAR ADDREss ADD BUS PT. 1 (can IOO-IY CONTRCI. INI4I PC1'B (RR) BUS PORT PARITY 00D PAR PTscaITINM) r" PORT -pcI3(wR] CONTROL m CONTROL T0 Heals-I6 PT.I,3,5coNT.IN(4I IN -Pc1B(PTI PT246c0NTINI4) MULTIPLEX (mm ADD BUS -MLTX I BITS oo-n AB(00|7) TO FIGS l3-l6 -MLTX 2 ADDRESS FROM TsTcIIIDIIAI ABIoo-m COLLECTOR Bus Hes-546 CLEAM'E) FIDs.Is-Is GATES (00) L MNN HEM. BK.I

AB(OO-l5l coNT. RET. 4 MEM. BUSY (IA) -I- 6 m "MN "EM 5K2 MEMORY DATA PA: (I CONT RH 4 CONTROL AVAILABLE IA sToRED RETURN FR"F|$13"5E' ED BNK SEL. :8 3 BUS LOADED IA I4 l5 I6 MULTIPLEX P7-P8 BUS BANK END OF ENABLE SELECT TO FIGS I3-l6 NAIN IAENI. BK.4 5I4 c\WLE M A P8 BUS L CONT. RET. 4 -END OF ENABLE MULTIPLEX MAIN, coNT LOGIC TEsT REG CYCLE T CLR NAIN NIENIcoNTRoL RETURN 4 IIAIN CONTROL FROM CMC-B RETURN TO FROM 5" ADDREss BUS sDuRcE ENABIE FIGSIIIAIS [3!6 l-PT RIIR ENABLE fIPDRT P8) MAIN M12! BK 4 U.S. Patent 0m. 28, 1975 Sheet 10 of 21 3,916,384

Fl 7 TO DATA aus MCB COMP AB O0-l5 E BIT X BIT [6 an PARITY DATA FROM CMC BJ COMPARATOR CHECK ADD CONTROL BUS S N IPA R E E S Bustools, LOGIC MULTIPLEX F PAR ADD t FROM MCL INVERTER BUS MAINT. DATA BUS ENABLE (00-0?) MNTH] MDBSO FROM MAB7 P7+P8 BUS ENABLE FROM ADD W 09 I7 -2MCL42 BUS E BITS |4 |5 BANK Afaz l s l-ft SELECT BUS MEN.

I 'AQBNKSELIS (0006) BK I "DDRESS A0 Bug IN AD,BNK.SEL.I5 (07PM) "ULT'PLEX -AD,BNKSEL.I6

INVERTER mm ow PAI (I?) I I A A THUS ERoM ADD BUS MEM. L STORED W ENABLE W42 VIoo-os) K2 PARITY BUS ADD BUS 8mm NABLE $0M42 "(OI-I4) L PAI (l6) j STORED BITHSD k MAIN I004 ADD aus MEN "(00-06) DDRESS OUT anus) .-o1= RANGE Bus PAI (I5) &

BITIIM PAI(|4) I E I I I R I003 ADD BUS lag:

I I II I I STORED N, BK. SELECTION :8

r us

-& L 4) i i n? STRAP AA,

STORED '7 JE l X'Q AoR BT04) iL X BS(3)HA) T PULSE I ERoM PH2 3 m 85mm) ,fig'gg MCL AF'A G If I I I l ADD BUS 0s STRAP DRUM N ITS I006 T0 coNTRoL G,K'Q, -LATcHEs REG.-PSPR(I-6) I007 MEM ARII4I B|,B2, B3, B4 FR MC DRUM OUTSIDE -DOBTA ALIAM IN ITIALIZATION -a- MCL PORT SELECT *1 TABLE BLOCK STRAP ;TRANS. AREA CMM BANK AR (l4) l,2,5,4 3 loos STRAP A0 SW.PROT READ READ ONLY ONLY MEM. ADD susuo-IsIuA MEMORY U.S. Patent Oct. 28, 1975 Sheetll0f2 $916,384

FIG.

Dcu(|,3,5l moeso CCP MDBSO BUS LATCH FROM DCU-l FROM DCU-3 FROM [ICU-5 we FROM ccP PORT mom cues 0A 7 RECEIVERS PORT 2,4,6

CCP M (23-25) PORT |,3 5 CABLE Ric. OUTPUTS m cums MLTPXI r0 cMc-a CCP T0 PORT) 0 251!) FOR CROSS 00-2 WRITE 6, mm

FROM MAIN MEMORY BKI FROM MAIN FROM MAIN FRO m MEN. K 2 HEM. BK. 3 mm. SK. 4

US. Patent Oct. 28, 1975 Sheet 19 0f21 3,916,384

F|G.I9

PORT SELECT PRIMARY REGISTER I 2 PSPR II) I |$T PRIORITY MREQ I +MREQ 2 MREQ3 PSPRIZI PRIORITY PSPR I +PSPR 2 PSPR 3 -PSPR3 PS P R (3) PRIORITY MREQ3 PSPRI 4) 4TH PRIORITY MREO4 +MREO 5 +MREO 6 PS PR (5) SPR4+PSPR5 PRIORITY PSPR 6 

1. In a communication system, a memory control arrangement including a central processor means, main memory means having a plurality of addressable data storage locations for storing data and program instructions for said central processor means, at least one auxiliary memory means for storing further instructions for said central processor means and memory control means for providing memory access control to permit the transfer of data between said main memory means either and said central processor means or said auxiliary memory means, said memory control means having a plurality of input/output ports including separate ports for said auxiliary memory means and said central processor means, port select means including first means for initiating a first main memory access cycle to enable one of said auxiliary memory means or said central processor means to address a data storage location of said main memory means to permit readout or modification of the program instruction or data stored at the addressed main memory means location, and second means for controlling said first means to initiate a second main memory access cycle for a different one of said auxiliary memory means or said central processor means prior to the termination of said first memory access cycle.
 2. A system as set forth in claim 1 wherein said first means includes port select primary register means including an individual port select primary register for each port of said memory control means, each of said port select primary registers having a plurality of inhibit inputs, the inhibit inputs of said port select primary registers being interwired to provide selection of a port on a priority basis in the event of simultaneous memory requests from said auxiliary memory means and said central processor means.
 3. A system as set forth in claim 1 wherein said first means includes port select primary register means including an individual port select primary register for each of said ports and said second means includes port select secondary register means including an individual port select secondary register for each of said port select primary registers, the one of said port select primary registers of the selected port being set responsive to the receipt of a memory request for such port to initiate a memory access cycle to permit access of the main memory means by said selected port, said one port select primary regisTer inhibit being operable when set to the remaining port select primary registers to preclude the initiation of a further memory access cycle by one of the remaining ports while said one port select primary register is set, the port select secondary register corresponding to said one port select primary register being set by said one port select primary register at a predetermined time during said first memory access cycle, and said one port select primary register being reset at such time to enable selection of a different one of said ports to permit a further memory access cycle to be initiated prior to the termination of the first memory access cycle.
 4. A system as set forth in claim 3 wherein said second means includes means for inhibiting said one port select primary register until a second port has been selected, for a further memory access cycle.
 5. A system as set forth in claim 4 wherein said auxiliary memory means includes at least one rotating drum memory means. 